We allocate a bias current of $960 \mu \mathrm{~A}$ to $M_1-M_8$, leaving $40 \mu \mathrm{~A}$ for the bias branches that generate $V_{b 1}$ and $V_{b 2}$. Let us split the current budget equally between the first and second stages, i.e., assume that $I_{D 1}=\cdots=I_8=120 \mu \mathrm{~A}$.



Since the second stage is likely to provide a voltage gain of 5 to 10 , the output swing of the first stage need not be large. Specifically, if the second stage is designed for a gain of 5 and a single-ended output swing of $0.5 \mathrm{~V}_{p p}$, the first stage need only sustain $0.1 \mathrm{~V}_{p p}$ at $X$ (or $Y$ ). The choice of overdrive voltages for $M_1-M_4$ and $I_{S S}$ is therefore quite relaxed, i.e., $\left|V_{O D 3}\right|+\left|V_{O D 1}\right|+V_{I S S}=1 \mathrm{~V}-0.1 \mathrm{~V}=0.9 \mathrm{~V}$. But we must consider two points: (1) recall from Chapter 7 that the noise contributed by current sources $M_3$ and $M_4$ is minimized by maximizing their overdrive voltage, and (2) the gain (and noise) requirements dictate a high $g_m$ for $M_1$ and $M_2$ and, inevitably, a low overdrive voltage. In fact, the latter point typically translates to subthreshold operation for the input devices, yielding a maximum $g_m$ of $I_D /\left(\xi V_T\right) \approx(325 \Omega)^{-1}$ with $\xi=1.5$. But, we ignore subthreshold operation in this example.



How large can the overdrive of $M_3$ and $M_4$ be? Since $V_{D S 3,4}=V_{G S 5,6}$ in this case, the upper bound may be imposed by $M_5$ and $M_6$ rather than by the first stage. For example, if the design of the second stage eventually yields $\left|V_{G S 5,6}\right|=400 \mathrm{mV}$, and if $V_X$ (or $V_Y$ ) can rise by 50 mV (for a $100-\mathrm{mV}_{p p}$ swing), then $M_3$ and $M_4$ experience a minimum $\left|V_{D S}\right|$ of 350 mV . We must therefore revisit this allocation after the second stage is designed.



For a single-ended output swing of $0.5 \mathrm{~V}_{p p}$, we can choose 200 mV and 300 mV for the overdrives of the output NMOS and PMOS devices, respectively. With $I_D=120 \mu \mathrm{~A}$, we then compute the $W / L$ values of these transistors. However, this allocation faces two issues: (1) the large overdrive of $M_5$ and $M_6$ may translate to an inadequately low $g_m=2 I_D /\left(V_{G S}-V_{T H}\right)$, and (2) the small overdrive of $M_7$ and $M_8$ gives them a high noise current. For these reasons, we swap the overdrive allocation, giving 300 mV to $M_7$ and $M_8$ and 200 mV to $M_5$ and $M_6$. The penalty is the larger $W / L$ of the latter pair and hence a greater capacitance at $X$ and $Y$.

We begin the calculations from the output stage. With $\left|I_D\right|=120 \mu \mathrm{~A}$ and the above overdrives, we have $g_{m 5,6}=2\left|I_D /\left(V_{G S}-V_{T H}\right)\right|=(833 \Omega)^{-1}, r_{O 5,6}=1 /\left(\lambda\left|I_D\right|\right)=42 \mathrm{k} \Omega$, and $r_{O 7,8}=83 \mathrm{k} \Omega$ (for the minimum channel length of $0.5 \mu \mathrm{~m}$ ). The second stage thus provides a gain of about 33, allowing even smaller voltage swings for the first stage. The corresponding device dimensions are $(W / L)_{5,6}=200$ and $(W / L)_{7,8}=44$.



Returning to the first stage in Fig. 9.23, we note that $V_{D S 3,4}=\left|V_{G S 5,6}\right|=550 \mathrm{mV}$. Transistors $M_3$ and $M_4$ can therefore operate with an overdrive as high as 500 mV (if we still assume $V_X$ or $V_Y$ can rise by 50 mV from the bias value) but require a $\left|V_{G S}\right|$ of $500 \mathrm{mV}+\left|V_{T H P}\right|=850 \mathrm{mV}$, and hence $V_{b 1}=150 \mathrm{mV}$. Such a low $V_{b 1}$ may cause difficulty in the design of the current mirror driving $M_3$ and $M_4$. Instead, we choose $\left|V_{G S 3,4}-V_{T H P}\right|=400 \mathrm{mV}$, obtaining $(W / L)_{3,4}=50, g_{m 3,4}=1 /(1.7 \mathrm{k} \Omega)$, and $r_{O 3,4}=83 \mathrm{k} \Omega$ (for $L=0.5 \mu \mathrm{~m}$ ).



The input transistors, $M_1$ and $M_2$, exhibit an output resistance of $83 \mathrm{k} \Omega$ (with $L=0.5 \mu \mathrm{~m}$ ) and can have an overdrive as large as 0.5 V . However, with such an overdrive, $g_{m 1,2} / g_{m 3,4}=\left|V_{G S 3,4}-V_{T H P}\right| /\left(V_{G S 1,2}-V_{T H N}\right)= 4 / 5$, implying that the PMOS devices contribute substantial noise. For this reason, we choose an overdrive of 100 mV for $M_1$ and $M_2$, arriving at $g_{m 1,2}=1 /(420 \Omega),(W / L)_{1,2}=400$, and a voltage gain of $g_{m 1,2}\left(r_{O 1} \| r_{O 3}\right)=66$ for the first stage.



This design provides an overall gain of more than 2,000 , primarily because of the low bias current and the use of an older technology.